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Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map - The Engineers' Daughter
While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance.... Read More