[ Authors ]
K. Prabha Rajeev, C. Opoku, V. Stolojan, M. Constantinou, F. Meyer, L. Chen, M. Shkunov
[ Abstract ]
Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the Si NW and the dielectric plays a crucial role in the FET performance, and it can be responsible for unwanted effects such as hysteresis of the I-V characteristics caused by the transistor threshold voltage shift when the gate voltage is applied. Using gate-voltage bias stress measurements and sweep-rate studies we show that a significant hysteresis of up to 40V in Si NW FETs with SiO2 dielectric is mainly due to the hole traps at the nanowire/SiO2 interface. We demonstrate a method for reducing hysteresis to only 2.5V by replacing SiO2 with a solution processable fluoropolymer dielectric Cytop. Finally, we demonstrate that nanowire surface trap density is dictated by the dielectric, by fabricating double gate FETs with bottom SiO2 and top Cytop gate insulators, where nanowire/SiO2 interface shows an order of magnitude higher trap density (1x10^13cm-2) compared to nanowire/fluoropolymer interface traps (7.5x10^11cm-2).