JTAG basic principle and performance comparison of the simulator

JTAG (Joint Test Action Group, jointly tests the action group) It is a kind of international standard measure agreement (IEEE 1149. 1 is compatible) . The interface of canonial JTAG is Line 4 - -TMS, TCK, TDI, TDO, it is mode selection, clock, data entry and DOL respectively.

There are two kinds of main functions of JTAG, mainly there are two major kinds of JTAG in other words: A kind of electric property used for test chip, find whether the chip has a question; Another kind is used in Debug, debug all kinds of chips and its peripheral devices. One CPU which contains JTAG Debug interface module, so long as the clock is normal, can visit the internal register of CPU, register of apparatus and built-in module hung on CPU bus line through JTAG interface. What this text mainly introduced is Debug function.

1 JTAG principle analysis

To be simple, the operating principle of JTAG can be come down to: Define one TAP (Test Access Port, tests the access port) within the device ,Test and debug the internal node through the dedicated JTAG testing tool. Basic conception and content of recommending a bottom circle to scan at first and TAP.

1. A border scanning

The boundry scans (Boundary-Scan) The technical basic thought is to increase a register unit of shifting on the I/O pin close to the chip, it is a boundry scan registor (Boundary-Scan Register) .

When the chip is in the debug mode, the boundry scan registor can isolate chip and peripheral I/O. Register unit it scan boundry,it can realize and input about chip /observation, outcoming signal and control. As to the input pin of the chip, can scan a signal (the data) of register unit through the boundry linking with it Load to this pin; As to the output pin of the chip, can ” catch ” through the boundry scan registor linking with it too Outcoming signal on this pin. Under the normal running status, the boundry scan registor is diaphanous for chip, so normal operation will not be influenced. In this way, the boundry scan registor has provided a convenient way for observing and controlling the required chip that debugs. In addition, the boundry on the chip I/O pin scans (shift) The register unit can be joined each other, form a boundry and scan the chain (Boundary-Scan Chain) around chip . Boundry can scan chain import and export serially, pass corresponding clock signal and control signal, can observe and control the chip that plays in debugging state conveniently.

1. 2 tests the access port TAP

TAP(Test Access Port) It is a general port, can visit all data registers (DR) that the chip offer through TAP And command register (IR) . The control on whole TAP is to pass TAP control device (TAP Controller) Come to finish. Introduce several interface signals and function of TAP separately first as follows. Among them, the first 4 signals are in IEEE1149. Require in a standard by force.

TCK: Clock signal, has offered an independent, fundamental clock signal for operation of TAP. TMS: The selective signal of the mode, are used for controlling the conversion of TAP state machine. TDI: Data input signal. TDO: Data outcoming signal. TRST: Reset signal, can be used for resetting TAP Controller (initialisation) . This signal interface is in IEEE 1149. Do not require in a standard by force, because can reset TAP Controller through TMS. STCK: The inverse signal of the clock, in IEEE 1149. It is required that optional in a standard. DBGRQ: The goal board divines the control signal of the working condition. In IEEE 1149. Have not required in a standard, just on the specific goal board (such as STR710) There will be China.

To be simple, the PC is finishing to the relevant data register (DR) through TAP interface to the debugging on board of the goal And command register (IR) Visit.

After systematic power up, TAP Controller enters Test-LogicReset state at first, then enter Run-Test/ Idle sequentially, Selcct-DR-Scan, Select-IR-Scan, Capture-IR, Shift-IR, Exitl-IR, Update-IR state, get back to Run-Tcst/ Idle state finally. In this course, the transformation of the state is driving through TCK signal (rising edge) ,Chose to change through the state of TMS signal pair TAP. Among them, under Capture-IR state, a particular logic array is loaded in the command register; Under Shift-IR state, can send a particular order to the command register; Under Update-IR state, the order input into the command register just now will be used for upgrading the command register. Finally, the system gets back to Run-Test/ Idle state again, the order comes into force, finishes the visit to the command register. After the system returns to Run-Test/ Idle state again, select the required data register according to the content of the preceding command register, begin to carry out the work to the data register. Its basic principle is exactly the same as his memory’s visit of the order, it is successively seIect-DR-Scan, Capture-DR, Shift-D, Exitl a DR, Update-DR, get back to Run-Tcst/ Idle state finally. Through TDl and TDO, can load the new data in the data register. After one cycle, can catch the data in the data register, finish the data updating to the chip pin linked with each register unit of the data register, also finished the visit to the data register.